1. Technical Field of the Invention
This disclosure relates to a semiconductor interconnection structure and a method of forming the same. More particularly, the disclosure relates to a semiconductor interconnection structure including a tantalum nitride (TaN) layer and a method of forming the same.
2. Description of the Related Art
A semiconductor device includes transistors, resistors, and capacitors. Interconnections between these elements are used to form the semiconductor device on a semiconductor substrate. The interconnections act as conductors for transmitted electrical signals. Therefore, the interconnections should have a low electrical resistance and be economical and reliable.
As semiconductor devices become more highly integrated, the width and thickness of interconnections are gradually reduced, and the size of contact holes is likewise decreased. This results in difficulty when forming interconnections.
FIG. 1 illustrates a cross-sectional view of a semiconductor interconnection structure according to a conventional method.
Referring to FIG. 1, an interlayer dielectric layer 2 is formed on a semiconductor substrate 1. A diffusion barrier layer 3, a conductive layer 5, an adhesion layer 7 and an anti-reflective layer 9 are sequentially stacked on the interlayer dielectric layer 2. The anti-reflective layer 9 is formed of titanium nitride (TiN), and the adhesion layer 7 is formed of titanium (Ti). The conductive layer 5 is formed of aluminum, and the diffusion barrier layer 3 is formed of titanium nitride (TiN). The anti-reflective layer 9, the adhesion layer 7, the conductive layer 5, and the diffusion barrier layer 3 are sequentially patterned by using a photoresist pattern in a photolithography process, to form sequentially stacked patterns 9, 7, 5 and 3. An interlayer dielectric layer 11 is formed to cover the patterns 9, 7, 5, and 3, and then patterned to expose the anti-reflective layer 9.
If a misalignment occurs during the photolithography process, the photoresist pattern should be removed by an ashing process, and a wet-cleaning process is carried out to remove organic residues remaining on the anti-reflective layer 9. Since a photoresist includes a photo acid generator (PAG) which generates an acid when exposed to light, an acid is generated by the photolithography process. Thus, when a subsequent cleaning process is performed, a cleaning solution is mixed with the generated acid to become a dilute acid.
Since aluminum, which is used for the conductive layer 5, has a property of being crystallized, a surface of the aluminum layer is not perfectly flat. That is, at the surface of the aluminum, a groove is formed at a boundary between crystallized aluminum grains. Thus, in a process of depositing titanium and titanium nitride on the surface of aluminum for the adhesion layer 7 and anti-reflective layer 9, respectively, it is difficult to deposit these layers at the groove. A titanium nitride deposited on the groove is thinner than that on the neighboring flat grains. Titanium nitride is chemically weak with respect to the dilute acid solution. Therefore, during the cleaning process, the thin and weak titanium nitride at the groove may be removed to expose titanium due to the weak chemical resistance. Also, the cleaning solution may damage or remove the exposed titanium and aluminum at the groove. Thus, the groove may get deeper. In this state, if a photoresist is coated again and a photolithography process is performed, the photoresist remains in the deepened groove to result in a ring defect along a boundary of an aluminum grain. The ring defect can cause a short between metal interconnections during operation of the semiconductor device, thereby lowering the reliability of a semiconductor device.
Furthermore, as space between interconnections is reduced due to the increased integration density of semiconductor devices, there is a limit to the method of forming a metal interconnection by using a photoresist pattern alone. To overcome this problem, an oxide pattern is formed on the anti-reflective layer of TiN and used as a hard mask to form a metal interconnection. But, this results in increased complexity to the overall process because an oxide pattern is additionally deposited and removed in a subsequent step.
In a multilayered interconnection structure of a semiconductor device, a via plug is formed to connect a bottom interconnection with an upper interconnection. When a via hole is formed for this purpose, only an anti-reflective layer on the bottom interconnection is exposed, or a conductive pattern of the bottom interconnection may be exposed. When the conductive pattern of the bottom interconnection is exposed, there may be a problem in a reliability of the bottom interconnection. The conductive pattern is generally formed of aluminum. When the aluminum is exposed, aluminum atoms migrate and crystallize to form grains in the surface of the aluminum. Thus, grooves are formed at the boundaries of the grains. The grooves between the aluminum grains are too fine to be filled in using a subsequent via hole-filling process. The very fine voids formed in this manner cause a problem in the reliability of the interconnection. Therefore, when the via hole is formed, only an anti-reflective layer is generally and preferably exposed.
However, an oxide intermetal dielectric layer 11 has a low etch selectivity with respect to the titanium nitride layer 9. Thus, when a via hole 13 is formed to expose the anti-reflective layer 9, the titanium nitride layer 9 may also be etched, as shown in FIG. 1. In addition, the etching may be so severe as to expose the aluminum layer 5. In order to prevent the aluminum layer 5 from being exposed, a relatively thick titanium nitride layer 9 is typically required. Since the titanium nitride layer 9 is thick, the total height of the interconnection becomes excessive and it is difficult to fill the space between the interconnections with the intermetal dielectric layer 11.
Embodiments of the invention address these and other problems with convention processes.